1. Field of the Invention
The present invention relates to a liquid crystal display device and a method of manufacturing the same, and more particularly, to a liquid crystal display device and a method of manufacturing the same, capable of reducing processes required to manufacture an LCD and capable of obtaining a storage capacitance, thereby providing an improved display quality.
2. Description of the Related Art
A liquid crystal display module is gaining importance as an information display device. A cathode ray tube (CRT) has advantages in performance and has been widely used until now. However, the CRT display device also has disadvantages in miniaturization and portability.
In order to overcome such disadvantages of the CRT, a liquid crystal display device (LCD) has been introduced. The LCD has many advantages such as being light, thin, and small, and having a high brightness and a large screen. The LCD also has low power consumption and a low price.
The LCD has a superior display resolution compared with other flat panel display devices and has a fast response speed compared with the CRT when a moving image is displayed.
LCD technology has been studied to develop an LCD to overcome a narrow viewing angle, and various schemes have been introduced such as an in-plan switching mode (IPS) and an optically compensated birefringence mode (OCB).
In the IPS mode LCD, two electrodes are formed on a same substrate, i.e., a bottom substrate. An electric field is generated in a horizontal direction with respect to the substrate as two electrodes supply a voltage therebetween in order to drive liquid crystal molecules horizontally from the substrate.
Therefore, in the IPS mode, a major axis of a liquid crystal molecule is not raised in a vertical direction with respect to a substrate, as in a twisted nematic (TN) mode.
As a result, the IPS mode LCD has a superior viewing angle compared with a TN mode LCD because the IPS mode LCD has a small variation of birefringence index of the liquid crystal according to the viewing angle.
The bottom substrate is generally called a thin film transistor (TFT) substrate, and the TFT substrate is manufactured using five to six mask processes. The number of mask processes directly relates to the manufacturing cost of the LCD. A method of manufacturing an LCD using four mask processes has also been used.
FIG. 1 is a plan view of an IPS mode LCD according to the related art.
As shown in FIG. 1, a unit pixel region is defined by a gate line 11 and the data line 13 which are arranged to cross each other. The gate line 11 receives a driving signal and the data line 13 receives data signals.
A common line 17 is arranged in parallel to the gate line 11 and is separated from the gate line 11 by a predetermined difference. A thin film transistor (TFT) is disposed as a switching element on a crossing region where the gate line 11 and the data line 13 cross.
In the unit pixel region, a plurality of common electrodes 18 is branched in a form of a slit, and a plurality of pixel electrodes 19 are alternately arranged with the common electrodes 18. The common electrodes 18 and the pixel electrodes 19 are separated by a predetermined distance.
The plurality of common electrodes 18 is arranged at a unit pixel region and extends from a first storage electrode 17b. The first storage electrode is integrally formed with the common line 17.
The pixel electrodes 19 extend from a second storage electrode 15, which is formed on the first storage electrode 17b to overlap with the first storage electrode 17b. 
A gate pad 11a is formed at an edge of the gate line 11 and a gate contact pad 21 made of transparent metal is formed on the gate pad 11a. 
A data pad 13a is formed at an edge of the data line 13 and a data contact pad 23 made of transparent metal is formed on the data pad 13a. A reference numeral 17a denotes a common pad.
FIGS. 2A through 2D are sectional views of FIG. 1 taken along a line I-I′ for describing a method of manufacturing an LCD according to the related art.
Referring to FIG. 2A, a metal layer is deposited on an insulation substrate 10. The gate line 11, the gate pad 11a and the gate electrode 3 and the common line 17 are simultaneously formed by an etching process.
The common line 17 is used as the first storage electrode 17b to form a storage capacitance Cst in a unit pixel region as shown in FIG. 1.
After forming the gate line 11, a gate dielectric layer 2 is formed on the entire surface of the insulation substrate 10.
Then, an amorphous silicon layer 4, a doped amorphous silicon layer 5 and a metal layer 7 are sequentially formed on the insulation substrate 10 as shown in FIG. 2B.
A photoresist is coated on the entire surface of the insulation substrate 10, and a half tone pattern is formed using diffractive exposure.
As shown in FIG. 2C, two etching processes are performed along the half tone pattern to form a channel layer 4a, an ohmic contact layer 5a, a source/drain electrode 13, 14 and a data line 13, simultaneously.
As shown in FIG. 1, the source electrode 13 is not additionally patterned or etched, and the data line 13 at the crossing region of the gate line 11 is used as the source electrode 13.
When the TFT is formed on the insulation substrate 10, a passivation layer 9 is formed on the entire surface of the insulation substrate 10 as shown in FIG. 2D.
After forming the passivation layer 9, a contact hole process is performed to open a predetermined portion of the drain electrode 14, the gate pad 11a, the data pad 13a and the common pad 17b. 
Then, a transparent metal is deposited on the insulation substrate 10, and the pixel electrode 19 and the second storage electrode 15 are integrally formed to overlap with the first storage electrode 17b. 
A gate contact pad 21 and a data contact pad 23 are formed on the data pad 13a as shown in FIG. 1.
However, it is very difficult to obtain the storage capacitance Cst in the LCD shown in FIG. 1 because the gate insulating layer 2 and the passivation layer 9 are formed between the first storage electrode 17b and the second storage electrode 15.
If the storage capacitance Cst is not sufficiently obtained, as in the related art, display quality of the LCD is degraded. Accordingly, the distance between the first storage electrode 17b and the second electrode 15 must be very short to sufficiently obtain the storage capacitance Cst. Also, the number of mask processes needs to be reduced to reduce the manufacturing cost of the LCD.